Dual gate oxide process for uniform oxide thicknessA process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprisingHelmut Horst TewsMary WeybrightStephan Kudelka
The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously. 展开
Breakdown voltage (V) and charge to breakdown (Q) are two parameters often used to evaluate gate oxide reliability.In this paper,we investigate the effects of measurement methods on V and Q of the gate oxide of a 0.18μm dual gate CMOS process.Voltage ramps (V-ramp) and current ramps (...
The method provided by the present invention affords a technique for ultra thin dual gate oxides having different thicknesses using a low temperature process in which no etching steps are required. The method includes forming a pair of gate oxides to a first thickness, which in one embodiment, ...
Dual damascene CMP process with BPSG reflowed cont 优质文献 相似文献 参考文献 引证文献High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization A high density Embedded DRAM technology has ...
Degradation of the ultrathin gate oxide process can be well visualized by the generation and increase of SILC. Before oxide breakdown happens, both p+/pMOS and n+/nMOS demonstrated the partial recovery of degradation after the withdrawal of stress voltage but before the oxide breakdown. A solid...
gate oxide 45 or the n-region and p-region of the substrate that will become the channel region of the NMOS and PMOS devices are not exposed through the mask. The process of the present invention is advantageous because it allows the PMOS and NMOS devices to be a distance apart that is...
Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs) A novel complementary metal-oxide-semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor ... S Kang,DH Kim,IH Park,... - International Conference on Solid State Devices ...
metal gatework functionaluminum nitrideWe evaluated the feasibility of using an ultra thin aluminum nitride (AlN) buffer layer for dual metal gates CMOS process. Since the buffer layer should not affect the thickness of gate dielectric, it should be removed or consumed during subsequent process. ...
Purpose – This paper aims to discover the novelties in biosensor fabrication brought about by breakthroughs in nanomaterials and process techniques, the r... Khanna,V Kumar - 《Sensor Review》 被引量: 35发表: 2008年 Organometallic Approach for Platinum and Palladium Doping of tin and tin Oxide...