A method for reordering a scan chain so that the given constraints are met and the peak power dissipation is minimized and disclosed. The constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The developed tool ...
The trade-off between our power-driven scan-cell reordering and a routing-driven scan-cell reordering is discussed based on experiments as well. 展开 关键词: correlation scan-chain reordering signal transitions 会议名称: IEEE Vlsi Test Symposium ...
Scan chain reordering is widely used method to reduce test power. In this paper, a Hamming distance based distributed reordering for loading and unloading scan chain vector is proposed. This method focuses on how and where weighted transitions occur. In current scenario of VLSI the manufacturing ...
10.3Scan chain diagnosis Scan chainstructures are widely used inVLSIcircuits under design for testing. They increase the fault coverage and diagnosability by enhancing the controllability andobservabilityof the digitalcircuit logic[362].Fig. 13shows the design of a preliminary scan chain. During normal...
1 Introduction and Motivation In VLSI design for testability, a scan chain is commonly used to connect the shift registers that store the input and output vectors during the testing phase of manufacturing. Registers in the scan chain are connected as a single path, with ends of the path ...
22. W. Li, S. Wang, S. T. Chakradhar and S. M. Reddy, “Distance restricted scan chain reordering to enhance delay fault coverage,” in Proc. Int. Conf. on VLSI Design, pp. 471-478, 2005. Google Scholar 23. P. Gupta, A. B. Kahng, I. Mandoiu, P. Sharma, “Layout-aware ...
In order to reduce the number of input constraints needed to achieve very high fault coverage, the present invention may involve a broadcast scan chain reordering step before ATPG takes place. Our approach is to perform input-cone analysis from each cone output (scan cell input) tracing backwards...
On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity i... CY Lin,LC Hsu,HM Chen - 《Ieice Trans...
Test Point Insertion and Scan Chain Reordering for 优质文献 相似文献 参考文献 引证文献Scan power reduction through test data transition frequency analysis Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may resul...
The main goal of this paper is to prove that recent technologies impose a new design flow, exploiting layout information for scan chain reordering. Two algorithms are then described, which reduce both the average and the maximum distance between FFs in the chains, thus reducing the power ...