VOP_CTRL_SET(vop,pin_pol,val); if(vop->dclk_source&&s->pll&&s->pll->pll) { if(!clk_set_parent(vop->dclk_source,s->pll->pll)) if(clk_set_parent(vop->dclk_source,s->pll->pll)) DRM_DEV_ERROR(vop->dev, "failed to set dclk's parents\n"); ...
> > > operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag > > > set. In that case it's usually possible to find a parent up the tree > > > which is capable of setting the rate (div, pll, etc). Implement a simple > > > lookup procedure for such cases, ...
C200HW-CLK21*1 C200H-OD211*1 C200H-ID212*1 C200H-MR431*1 Stock: 6 pcs Warranty:One year
> > > > operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag > > > > set. In that case it's usually possible to find a parent up the tree > > > > which is capable of setting the rate (div, pll, etc). Implement a simple > > > > lookup procedure for ...