可以使用clk_register_gate()函数注册一个时钟门控器,在使用时可以通过clk_enable()和clk_disable()函数控制时钟的使能状态。 Mux Clock(时钟选择器):从多个输入时钟中选择一个作为输出时钟。可以使用clk_register_mux()函数注册一个时钟选择器,在使用时可以通过clk_set_parent()函数设置该时钟的父时钟。 Divider ...
实现.recalc_rate,.set_rate和.round_rate。 常用API: clk_register_divider()/clk_unregister_divider() clk_hw_register_divider()/clk_hw_unregister_divider() 8、struct clk_mux struct clk_mux用于描述多路复用器的时钟,该结构定义如下: struct clk_mux { struct clk_hw hw; void __iomem *reg; cons...
这一类clock可以选择多个parent,因为会实现.get_parent/.set_parent/.recalc_rate回调。该接口可注册mux控制比较规则的clock(类似divider clock): name:clk名字; parent_names:一个字符串数组,用于描述所有可能的parent clock名字; num_parents:parent clock的个数; reg、shift、width,选择parent的寄存器、偏移、宽度,...
.get_parent = clk_dummy_single_get_parent, };struct clk_multiple_parent_ctx { struct clk_dummy_context parents_ctx[2]; struct clk_hw hw; u8 current_parent; };static int clk_multiple_parents_mux_set_parent(struct clk_hw *hw, u8 index) ...
struct clk *parent; struct clk **dependence; u32 dependence_count; u32 div; u32 mul; const struct clk_mux_sel *inputs; struct { void __iomem *reg; u32 reg_shift; u32 reg_mask; } reg_data[REG_TYPE_NUM][REG_CONTROL_NUM]; ...
int(*set_rate)(structclk_hw*hw,unsignedlong, unsignedlong); void(*init)(structclk_hw*hw); }; 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 多路时钟源: structclk_mux{ structclk_hwhw;//指向硬件时钟结构体 ...
Remove CLK_SET_PARENT from all MSDC core clocks clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag clk: mediatek: Enable all MT8192 clocks by default * clk-i2cid: clk: rs9: Fix .driver_data content in i2c_device_id clk: vc7: Fix .driver_data content in i2c_device_id clk...
const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); 4.mux clock 这一类clock可以选择多个parent,因为会实现.get_parent/.set_parent/.recalc_rate回调,可通过下面两个接口注册: ...
226 ERROR("The parent of the PLL isn't a MUX\n"); 227 return NULL; 228 } 229 230 return s32cc_obj2clkmux(source); 231 } 232 233 static void disable_odiv(uintptr_t pll_addr, uint32_t div_index) 234 { 235 mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PL...
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definations in the common clock framework to public header clk-provider.h, and drop the local definations.