可以使用clk_register_gate()函数注册一个时钟门控器,在使用时可以通过clk_enable()和clk_disable()函数控制时钟的使能状态。 Mux Clock(时钟选择器):从多个输入时钟中选择一个作为输出时钟。可以使用clk_register_mux()函数注册一个时钟选择器,在使用时可以通过clk_set_parent()函数设置该时钟的父时钟。 Divider ...
实现.recalc_rate,.set_rate和.round_rate。 常用API: clk_register_divider()/clk_unregister_divider() clk_hw_register_divider()/clk_hw_unregister_divider() 8、struct clk_mux struct clk_mux用于描述多路复用器的时钟,该结构定义如下: struct clk_mux { struct clk_hw hw; void __iomem *reg; cons...
这一类clock可以选择多个parent,因为会实现.get_parent/.set_parent/.recalc_rate回调。该接口可注册mux控制比较规则的clock(类似divider clock): name:clk名字; parent_names:一个字符串数组,用于描述所有可能的parent clock名字; num_parents:parent clock的个数; reg、shift、width,选择parent的寄存器、偏移、宽度,...
ops->get_parent = ti_adpll_clkout_get_parent; ops->determine_rate = __clk_mux_determine_rate;if(gate_bit) { co->gate.lock = &d->lock; co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; co->gate.bit_idx = gate_bit; ops->enable = ti_adpll_clkout_enable; ops->disable = ti_...
+ .set_parent = _omap4_mux_mod_set_parent, + .determine_rate = _omap4_mux_mod_determine_rate, +}; + +static void __init _of_ti_omap4_hwmod_mux_clk_setup(struct device_node *node, + u8 modulemode) +{ + struct clk_hw_omap *gate; ...
int(*set_rate)(structclk_hw*hw,unsignedlong, unsignedlong); void(*init)(structclk_hw*hw); }; 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 多路时钟源: structclk_mux{ structclk_hwhw;//指向硬件时钟结构体 ...
> > > > operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag > > > > set. In that case it's usually possible to find a parent up the tree > > > > which is capable of setting the rate (div, pll, etc). Implement a simple ...
clk_parent = clk_get(dev->device,"oscclk");if(IS_ERR(clk_parent)) { clk_put(clk_child); clk_put(clk_old_parent); pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));returnPTR_ERR(clk_parent); }/* before set mux register, all source clock have to enabled */...
const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); 4. mux clock 这一类clock可以选择多个parent,因为会实现.get_parent/.set_parent/.recalc_rate回调,可通过下面两个接口注册: ...
struct clk *parent; struct clk **dependence; u32 dependence_count; u32 div; u32 mul; const struct clk_mux_sel *inputs; struct { void __iomem *reg; u32 reg_shift; u32 reg_mask; } reg_data[REG_TYPE_NUM][REG_CONTROL_NUM]; ...