可以使用clk_register_mux()函数注册一个时钟选择器,在使用时可以通过clk_set_parent()函数设置该时钟的父时钟。 Divider Clock(时钟分频器):将输入时钟的频率分频后得到输出时钟。可以使用clk_register_divider()函数注册一个时钟分频器,在使用时可以通过clk_set_rate()函数设置该时钟的频率。 Fractional-N PLL Clo...
int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index);...
VOP_CTRL_SET(vop,pin_pol,val); if(vop->dclk_source&&s->pll&&s->pll->pll) { if(!clk_set_parent(vop->dclk_source,s->pll->pll)) if(clk_set_parent(vop->dclk_source,s->pll->pll)) DRM_DEV_ERROR(vop->dev, "failed to set dclk's parents\n"); ...
clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); }else{ clk_set_parent(mali_parent_clock, mpll_clock); clk_set_parent(mali_clock, mali_parent_clock); }if(clk_enable(mali_clock) <...
int clk_set_parent(struct clk *clk, struct clk *parent); struct clk *clk_get_parent(struct clk *clk); struct clk *clk_get_sys(const char *dev_id, const char *con_id); int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, struct device *dev); ...
parent - clk是由parent分出来的。那么如果parent关闭了,当前clk也就没有了。 secondary - 第二时钟源,用于enable/disable当前clk。 usecount - 引用计数。 get_rate, set_rate, enable, disable, set_parent - 很显然,这些函数指针指到实际操作的函数。clk.h中的各接口函数最后都会调用到这里的函数指针。函数...
.clk_set_parent= omap2_clk_set_parent, .clk_get_parent= omap2_clk_get_parent, .clk_disable_unused= omap2_clk_disable_unused, #ifdef CONFIG_CPU_FREQ .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, #endif }; 初始化clk模型: ...
> > its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in > > the clock driver [2]. So the right thing to do in this case (and > > that's basically how it's done in Linux kernel too) is to traverse the ...
示例13: tegra_das_set_mclk_parent ▲点赞 1▼ inttegra_das_set_mclk_parent(intparent){/* FIXME ; set parent based on need */structclk*mclk_source=clk_get_sys(NULL, "pll_a_out0");clk_set_parent(aud_manager->mclk, mclk_source);return0; ...
* the parent of another without actually changing the parent. * * Returns true if @parent is a possible parent for @clk, false otherwise. */ bool clk_has_parent(struct clk *clk, struct clk *parent); /** * clk_set_rate_range - set a rate range for a clock sour...