}if(clk_get_parent(clk) != parent_clk) clk_set_parent(clk, parent_clk);if(parent_clk != clk_get_sys(NULL,"pll_p")) {structclk*base_clk=clk_get_parent(parent_clk);/* Assuming either pll_d or pll_d2 is used */rate = dc->mode.pclk *2;if(rate != clk_get_rate(base_clk...
- parent_names[i] = of_clk_get_parent_name(data->node, i); - - clk = data->clk_register_get(data->node->name, parent_names, - num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW); + clk = data->clk_register_get(data->node->name, data->parent_names, + data->num_parents,...
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