int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index);...
&imx93_clk_composite_divider_ops, gate_hw, &imx93_clk_composite_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); } else { hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &imx93_clk_composite_mux_ops, div_hw, &imx93_clk_composite_divider_ops, NULL, ...
unsigned long old_rate; unsigned long best_parent_rate = 0; struct hlist_node *tmp;old_rate = clk->rate;if (clk->parent)best_parent_rate = clk->parent->rate;if (clk->ops->set_rate)clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate);clk...
void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_...
> The driver is currently only tested on Tegra124 Jetson TK1, but should > work with other Tegra124 boards, provided that correct EMC tables are > provided through the device tree. Older chip models have differing > timing change sequences, so they are not currently supported....
if (clk_core_rate_is_protected(core)) return -EBUSY; trace_clk_set_duty_cycle(core, duty); if (!core->ops->set_duty_cycle) return clk_core_set_duty_cycle_parent_nolock(core, duty); ret = core->ops->set_duty_cycle(core->hw, duty); if (!ret) memcpy(&core->duty, duty, siz...
parent_names = (const char*[]) { "gcc_aggre1_ufs_axi_clk" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_hw_ctl_ops, }, }, }; Given that both clocks have the same enable_reg and enable_mask, they alias each other. The ufshcd driver only uses ...
structclk_hw*hw;//对应时钟硬件操作 structclk*parent;//时钟的父亲 constchar**parent_names;//当前时钟的父亲名称 structclk**parents;//当前时钟有多个父时钟源 u8num_parents;//时钟源个数 unsignedlongrate;//频率 unsignedlongnew_rate; unsignedlongflags; ...
(*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index)...
init.parent_data = parent_data; if (parent_name || parent_hw || parent_data) init.num_parents = 1; else init.num_parents = 0; /* struct clk_gate assignments */ gate->reg = reg; gate->bit_idx = bit_idx; gate->flags = clk_gate_flags; gate->lock = lock; gate->hw.init =...