Learn about designing a multiplexer in verilog with example code, specifically a 4x1 or 4 to 1 mux
What is the problem is using assign statements for a comparator design (it can be done since this comparator of yours doesn't need to be sequential)? Code: module comparator( a, b, c ); input [7:0] a,b; output reg c; //reg c; //wire c; //assign c=(a==b)?1:0; alwa...