4.The memory interface latch of claim 1, wherein the data NAND gate is a 3-input NAND gate having a first input coupled to the bitline of the memory array, a second input coupled to an additional bitline of the memory array, and a third input coupled to the feedback node, the data...
Get a RTL schematic using a toolchain like Vivado to find out what the inputs and outputs of the FPGA are used for (UART TX/RX, reset, clock). Code a testbench in Verilog to be able to communicate with the FPGA over UART and send/receive data -> it encrypts 8-byte blocks and se...