mux_assign.v / Verilog 1/* 2(C) OOMusou 2010http://oomusou.cnblogs.com 3 4Filename : mux_assign.v 5Simulator : NC-Verilog 5.4 + Debussy 5.4 v9 + Quartus II 8.1 6Description : mux by assign 7Release : Sep.22,2010 1.0 8*/ 9 10modulemux_assign ( 11a_i, 12b_i, 13c_i, 14...
5 Simulator : NC-Verilog 5.4 + Debussy 5.4 v9 + Quartus II 8.1 1. 6 Description : mux by case 1. 7 Release : Aug.30,2010 1.0 1. 8 */ 1. 9 1. 10 module mux_case ( 1. 11 a_i, 1. 12 b_i, 1. 13 c_i, 1. 14 d_i, 1. 15 sel_i, 1. 16 q_o 1. 17 ); 1....