Present invention suggests a method to extract accurate value and time domain of the current in the VLSI circuit, which is almost impossible by the conventional methods. Conventional approaches take the current
CMOS technology continues to drive the reduction in switching delay and power while improving area density. However, the transistor miniaturization also introduces many new challenges in Very Large Integrated (VLSI) circuit design, such as sensitivity to process variations, increasing transistor leaka...
标准单元(Standard Cell)是一般数字VLSI设计中的基本组件。整个数字电路逻辑设计,在逻辑综合与工艺映射中(这两者概念请参考),会被替换成一堆互相连接的标准单元。常见的Standard Cell有基本逻辑门(与、或、与非、亦或...)、Flip-Flop寄存器、MUX多路选择器、加法器、时钟单元、延时缓冲(Delay Buffer)等等。基于这些标...
The performance of the circuit, before and after radiation strike is compared using the metrics, write delay, read delay and the circuit's power consumption. It can be observed that Si/GaAs based 6T SRAM shows higher RSNM and WSNM whereas InAs based 6T SRAM shows lesser RSNM and WSNM. ...
Sapna Singh, Neha Arora, Meenakshi Suthar & Neha Gupta 2012, "Performance Evaluation of Different SRAM Cell Structures at Different Technologies'`, International Journal of VLSI design & Communication Systems (VLSICS), Vol.3, No.1, pp.97-109....
D. B. Schwartz, “ATM Scheduling with Queuing Delay Predictions”, http://ipoint.vlsi.uiuc.edu/wireless/papers-p/p205-schwartz.pdf. Timothy G. W. Gordon and Peter J. Bentley, “On Evolvable Hardware”, In Ovaska, S. and Sztandera, L. (Ed.) Soft Computing in Industrial Electronics. ...
The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.doi:10.5121/vlsic.2012.3304Ali GhorbaniMehdi SarkhoshElnaz FayyaziNeda MahmoudiPeiman KeshavarzianAcademy & Industry Research Collaboration Center (AIRCC)International Journal...
US6016315A|1997-04-30|2000-01-18|Vlsi Technology, Inc.|Virtual contiguous FIFO for combining multiple data packets into a single contiguous stream| KR100212064B1|1997-05-21|1999-08-02|윤종용|2n x n multiplexer switch architecture| US6301259B1|1997-05-26|2001-10-09|Mitsubishi Denki Ka...
of a design style relating to quasi-delay-insensitive asynchronous VLSI circuits. However it will be understood that many of the principles and techniques of the invention may be used in other contexts such as, for example, non-delay insensitive asynchronous VLSI as well as synchronous VLSI. ...
a delay to form a plurality of second sets of parallel signals of n bits, wherein said plurality of second sets are arranged in a series so that each of said second sets has a predetermined position within the series, and so that the bit order of each of said second sets is shifted ...