MutluAvci and SerhanYamacli , "An improved Elmore delay model for VLSI interconnects" , Mathematical and Computer Modelling 51 , 908-914 , 2010.A.Mutlu,Y.Serhan.An improved Elmore delay model for VLSI interconn
accurate delay models for coupled interconnects are very much required. This paper proposes an analytical model for estimating propagation delay in lossy coupled RLC interconnect lines for simultaneously switching scenario. To verify the proposed model, the analytical results are compared with those of FD...
First, we cover some of the common clock topologies used in VLSI circuits. Second, we present the Elmore delay model, which is extensively used in the EDA community for the analysis and synthesis of clock networks. Third, we describe several basic clock synthesis algorithms, dealing with both ...
Transmission gates are used extensively in CMOS VLSI circuits. However, very few delay models have been developed for transmission gates or transmission-gate-based circuits. Accurate delay models are presented in this paper and compared with delays obtained from SPICE simulations. These delay models ...
We model an asynchronous circuit C by a network N of modules with delays associated with its components and/or wires. We compute the behavior of N assuming arbitrary inertial delays in the modules, and take this behavior to be correct. We define N to be strongly delay-insensitive if its be...
Nishimaru, Y.Yoshida, N.INTEGRATION -AMSTERDAM-Tetsushi Koide,Shin ichi Wakabayashi,Mitsuhiro Ono,Yutaka Nishimaru,Noriyoshi Yoshida.A Timing-driven Placement Algorithm With the Elmore delay model for row-based VLSIs.Integration The VLSI Journal. 1997...
A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a simple lumped-circuit model is also described. The future trends of the GERDE are investigated and it is concluded that the GERDE gets ...
Naoya Onizawa,Tomoyoshi Funazaki,Atsushi Matsumoto, et al.Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. IEEE Annual Symposium on VLSI . 2010Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. Naoya Onizawa,Tomoyoshi Funazaki,Atsushi ...
VLSI DesignTheodoridis, G., Theoharis, S., Soudris, D. and Goutis, C.E. (2001) "A probabilistic power estimation method for combina- tional circuits under real gate delay model", VLSI Design, Journal of Custom-Chip Design, Simulation, and Testing 12(1), 69 - 79....
By uniting communication delays and the network interface, interface delay model was established for communication delays in network control system. 针对网络控制应用中的延迟问题,通过将传输延迟与网络接口合并到一起 ,建立了一种新模型 :接口延迟模型,然后给出了接口延迟的求解方法 ,并对接口延迟在实际应用中...