It should also be noted that specific embodiments of the invention are described in the context of a design style relating to quasi-delay-insensitive asynchronous VLSI circuits. However it will be understood that many of the principles and techniques of the invention may be used in other contexts...
Our method uses an accurate net weight calculation based on Elmore delay model. Experiments show that our timing model is very effective.Chapter 6 discusses how to integrate clustering schemes into our quadrisection based placement in order to speed up the execution time and improve the solution ...
In this paper, we propose an evolvable fuzzy system for ATM cell scheduling. When the scenarios of cell flows in an ATM network change dramatically, traditional scheduling algorithms, first-in-first-out (FIFO) and static priority, which employ static swi
Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test p
Covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verificat... J Bhasker,R Chadha - Springer Publishing Company, Incorporated 被引量: 153发表: 2009年 Variation-Driven Device Sizing for Minimum Energy Sub...
In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption ...
In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 ...
The basic approach followed for ECC is as follows: data bits’ encoding is followed by syndrome calculation using codes already implemented; then, the syndromes’ comparison locates the error bits. Errors correction is the last step to complete the rectification. Matrix ECCs are appealing because ...
2. The Basic Concept of Power Calculation and Optimization The energy consumed in an integrated circuit (IC) can be split into two main branches: A static power dissipation related to the logical states of the circuit. In CMOS logic, the leakage current and subthreshold current are the only...
1. Hollow Glass Microneedle Channel (Micropipette) Microneedles were fabricated by pulling borosilicate capillaries (BF100-50-10, Sutter, Linton Instrumentation, Norfolk, UK) using a micropipette puller (P-97, Sutter) programmed to a temperature of 289 (RAMP), pull 30, velocity 120 and delay ...