申请(专利权)人: VLSI TECHNOLOGY, INC.发明人:PH Sorrells,ND Garinger 被引量: 45 摘要: An output pad for an integrated circuit includes circuitry to fix the output delay to a constant value even when changes occur in power supply voltage, manufacturing process and temperature. This output ...
申请(专利权)人: FUJITSU LIMITED;FUJITSU VLSI LIMITED 发明人:T Seki,A Iwase,S Nagai 被引量: 14 摘要: A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected ...
In recent years, the design for low power has become one of the greatest challenges in high-performance verylarge scale integration (VLSI) design. Most of the methods focus on the power consumption during normal modeoperation, while test mode operation has not normally been a predominant concern...
Test generation in VLSI circuits for crosstalk noise Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the ... W Chen,S.K. Gupta,MA Breuer - International Test Conference 被引量: 297发表: 1998年...
In this paper, we adopt the hierarchical link sharing (HLS) algorithm in non-blocking CIOB switches to guarantee delay bound that is independent of the switch size. We also propose a feasible architecture to implement the HLS algorithm in the switch, which can accommodate the packet carried ...
A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a ... T Matano,Y Takai,T Takahashi,... - Symposium on Vlsi Circuits Digest of Technical Papers 被引量: 139发表: 2003年 A 1...
Due to its modularity the Gauss ASE can grow towards a large single-stage output buffered switch fabric that can offer low delays and low delay jitter and which is probably easier to manage. The suitability for VLSI has been shown; only two types of integrated circuits are needed. Inputs ...
A low-cost supply voltage supervisor IC, that includes a built-in time delay, is an ideal component for automatically controlling the Track inputs at power up. Figure 14 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequenced power up of two 12-V...
PURPOSE:To provide an input output circuit whose manufacturing process is simply in which a signal input having a voltage over a power supply voltage at all times is received and an input leakage current and an output delay are minimized. CONSTITUTION:The input output circuit is a circuit formed...
(Pico-farads) load can be used with only five memory chips, if the inputs of the memory chips offer a 10 pf load. To add more memory chips, another buffer chip to buffer the address which can drive more than five memories is needed. This adds extra delay in the signal propagation, ...