G., Effects of inductance on the propagation delay and repeater insertion in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(2): 195u206Y.I. Ismail and E.G. Friedman, "Effects of inductance on the propa- gation delay and repea...
AbstractBufferinsertionisaneffectiveapproachtoachievebothminimalclocksignaldelayandskewinhighspeedVLSIcircuitdesign.Inthispaper,wedevelopanopti-mal..
In: IEEE Computer Society Annual Symposium on VLSI, pp. 131–136, IEEE Press, Montpellier, France (2015) Google Scholar Elgamal, T.: A public key cryptosystem and a signature scheme based on discrete logarithms. IEEE Trans. Inf. Theory 31(4), 469–472 (1985) Article MathSciNet Google ...
intheinterconnectdesign.Techniqueswhichaimtoreduceintercon- nectdelayandpowerconsumptionarerequiredforhighspeedcircuit design. Repeatersarenowwidelyusedtodecreasethedelayandincrease theperformanceoflongon-chipinterconnectionsinCMOSVLSI.For largehigh-performancedesigns,thenumberofsuchrepeaterscanbe veryhighandcantakeupsig...
A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserti
Given a resource constraint, a 0–1 ILP formulation for resource-constrained link insertion is proposed to insert timing-driven geometrical links in a given rectilinear Steiner tree. The proposed 0–1 ILP formulation has 21.0% of the delay reduction under the resource constraints for 10% of the...
This invention relates to an automated approach for inserting delay elements into complex, high performance VLSI circuits to address hold time problems; and more particularly to development of an algorithm and CAD solution to insert delay elements ...
Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted. 展开 关键词:...
In VLSI interconnects, buffers are used to restore the signal level affected by the parasitic such as line capacitance, inductance, etc.. However buffers have a certain switching time that contributes to overall signal delay. Further, transitions that occur in interconnects give rise to crosstalk ...
Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic on such integrated circuit. Specific fault types programmable for each fault class include ...