Logic BIST通过将很多的tester functionality放在CUT中,减少了test costs,但是更重要的一方面是at-speed testing. At-speed test包括两部分: 1) intra-clock-domain fault:originates at one clock domain, terminate at the same clock domain 2) inter-clock-domain fault:originates at one clock domain, termina...
网络全速测试 网络释义 1. 全速测试 ...够最大限度地把测试过程集成在芯片内部,同时支持芯片全速测试(At-Speed-Testing),已成为解决芯片测试难题和降低测试成本 … cdmd.cnki.com.cn|基于 1 个网页
首先需要两个连续的at-speed时钟cycles。 在第一个时钟上升沿令path的起点产生一个跳变(例如0->1),在第二个时钟上升沿,如果能在终点捕捉到跳变后的值(这里是1),那么目标path能在一个系统周期完成数据传递,反之则该path有path delay故障。 对transition delay故障求解的过程也非常类似。 区别在于: 在第一个at-...
首先需要两个连续的at-speed时钟cycles。 在第一个时钟上升沿令path的起点产生一个跳变(例如0->1),在第二个时钟上升沿,如果能在终点捕捉到跳变后的值(这里是1),那么目标path能在一个系统周期完成数据传递,反之则该path有path delay故障。 对transition delay故障求...
1)at-speed test实速测试 1.At-speed test has been widely used in industry.实速测试在工业界中得到日益广泛的使用,对芯片进行实速测试可以有效检测出时序相关的故障。 2)experiment test实验测试 1.This article introduces the methods, the existent problems andthe suggestions on theexperiment testof entran...
At-speed Testing of SOC ICs Vlado Vorisek, Thomas Koch, Hermann Fischer Multimedia Design Center, Semiconductor Products Sector Motorola Munich, Germany Abstract This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some ...
Robert W. MossMark J. KwongPeter KorgerChristopher M. GilesUS7065683 * Dec 5, 2001 Jun 20, 2006 Lsi Logic Corporation Long path at-speed testingUS7065683 * 2001年12月5日 2006年6月20日 Lsi Logic Corporation Long path at-speed testing...
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-bas... N Ahmed,M Tehranipoor,CP Ravikumar,... - ...
testingreplacedfunctionaltesting.Andat-speedtestforbothlogicandmemoryisbecominga requirementtoensureacceptableDPMrates.Thispaperdiscussesthemethodologyofat-speedandthe clockgenerationcircuitsupportingat-speedtest———OCCcircuit. Keywords:At-speedtest;OCC;testclockgeneration;; ...
A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequ... TK Jaber,JJ Leblanc,RG Walther - US 被引量: 58...