main Axi_Can_Lite.cache Axi_Can_Lite.hw Axi_Can_Lite.ip_user_files Axi_Can_Lite.runs Axi_Can_Lite.sim Axi_Can_Lite.srcs .gitignore Axi_Can_Lite.xpr README.md vivado.jou vivado.log vivado_17072.backup.jou vivado_17072.backup.log ...
(答复记录 66860)Vivado Logic Debug [Labtools 27-1972] Mismatch between the design programmed into the device XXXX (JTAG device index = X) and the probes file path/impl_6/debug_nets.ltx2015.3 (答复记录 67062)当 Zynq 7000 PS 外设(如,GigE、D 等)的输出信号通过 MIO(FIXED_IO 总线)映射到 PS...
// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH // Tcl Message: program_hw_devices: Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 4650.301 ; gain = 16.211 // TclEventType: HW_DEVICE_CHANGE // TclEventType: HW_SYSMON_CHANGE...
INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug ...
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