查看设计文件中的module()括号里面的内容是不是是不是将“,”写成了“;”以及最后一个输入项后面不用写“,”。
70400 - Vivado IP Flows - Synthesizing a Block design in non-project mode fails with ERROR: [Synth 8-439] module '<hls IP submodule>' not found Description When I synthesize my design in Project mode, there are no errors. However, if I reset the output products of the IP in the desi...