rfi_detector finish arte resize tests Jun 10, 2022 utils single bin correlator tested in zuboard Jul 7, 2024 work_in_progress fix r22sdf test Jul 8, 2024 xlx_templates add primitives to xil_primitives Nov 26, 2023 .gitignore spiral fft spectrogram ...
dynamic_delay.svdynamic delay for arbitrary input signal 🟢edge_detect.svcombinational edge detector, gives one-tick pulses on every signal edge encoder.vdigital encoder input logic module 🔴fast_counter.svsynthetic counter fifo_combiner.svaccumulates data words from multiple FIFOs to a single out...
173 58 10 5 months ago Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/46 Verilog Generator of Neural Net Digit Detector for FPGA 168 7 1 1 year, 9 months ago fpga-chip8/47 CHIP-8 console on FPGA 165 169 1 4 months ago fpga/48 The USRP™ Hardware Driver FPGA Repository 163...
edge_detect.svcombinational edge detector, gives one-tick pulses on every signal edge encoder.vdigital encoder input logic module fifo.svsingle-clock FIFO buffer (queue) implementation gray2bin.svcombinational binary to Gray code converter leave_one_hot.svcombinational module that leaves only lowest ...
if it receives X=0 it stays at S0 else goes to S1 that indicate that first bit is detected .At S1 if it receives 1 it goes to S2 and output remains is Y=0 in both cases.In state S1 if it receives X=0 then output Y=1 hence all the three bit pattern has been received,if at...
173 58 10 5 months ago Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/46 Verilog Generator of Neural Net Digit Detector for FPGA 168 7 1 1 year, 9 months ago fpga-chip8/47 CHIP-8 console on FPGA 165 169 1 4 months ago fpga/48 The USRP™ Hardware Driver FPGA Repository 163...
2. Check lock-bit status.The lock bit is set only when Ffdbk=Fref, thus you can measure the frequency and time at which the lock bit is set. You determine the frequency at which the PLL locks using the vcd file and verify the lock-bit status with the pattern. ...
pattern_detector_fsm Change in intendation Jan 4, 2021 ram Added ram test code Jan 5, 2021 simple_alu Added simple alu Dec 26, 2020 system_tasks Added display tasks Dec 25, 2020 .gitignore Added binary files to ignore Dec 11, 2020 Makefile Changed default project Dec 27, 2020 readme....
verification_open_jtag_project testing-verification_bus_transaction_monitor_with_jtag testing-verification_pltbutils testing-verification_video_pattern_generator testing-verification_systemverilog_directed_test_bench testing-verification_generic_ahb_slave_stub testing-verification_prbs_signal_generator_and_checker ...
arte_stuffs : codes for a Radio transient detector backend.More info here. axi : AXI and AXI lite related codes. casper_utils : HDLs that are meanted to be used in the CASPER enviroment. Here you can found some examples. cocotb_python : Codes for handle signed fixed point input/outputs...