Our resultsindicate that while interface roughness effects can be substantial in the direct tunnelingregime, they are less important in the Fowler-Nordheim regime.D.Z.-Y.TingErikS.DanielT.C.McgillingentaconnectVlsi DesignD. Z.-Y. Ting, E. S. Daniel, and T. C. McGill, "Interface roughness...
The continuously intensifying demand for high-performance and miniaturized semiconductor devices has pushed the aggressive downscaling of field-effect transistors (FETs) design. However, the detrimental short-channel effects and the fundamental limit on the sub-threshold swing (SS) in FET have led to a...
The continuously intensifying demand for high-performance and miniaturized semiconductor devices has pushed the aggressive downscaling of field-effect transistors (FETs) design. However, the detrimental short-channel effects and the fundamental limit on the sub-threshold swing (SS) in FET have led to ...
Tech. Dig. VLSI Symp. 1–2 (2016). 29. Harris, C. & O'Reilly, E. P. Nature of the band gap of silicon and germanium nanowires, Physica E. 32, 341–345 (2006). 30. Guo, P.-F. et al. Tunneling field-effect transistor: effect of strain and temperature on tunneling current. ...
We describe modeling methods and results for a new technological process that combines the tunneling effect with cybernetic control methods to achieve further reduction of VLSI components to nanometer dimensions (tunneling lithography).doi:10.1007/BF01125548V. P. Derkach...
A new floating-body effect in advanced fully-depleted SOI MOSFETs is revealed. Gate tunneling current is responsible for the body charging and may lead to the onset of an abnormal peak in transconductance. This effect occurs even at low drain voltage, is gate area-dependent, and can be modula...
In: IEEE Symp VLSI Tech invited; 2015, p... Li M, Yan R, Jena D, Xing HG. Two-dimensional heterojunction interlayer tunnel FET (Thin-TFET): from theory to... A.M. Walke et al. Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET IEEE Trans Electron Dev (...
6.The tunnel field effect transistor of claim 1, wherein second peak concentration is a factor of 4 higher than the maximum doping level of the first doping profile at or close to the interface between the first source sub-region and the second source sub-region. ...
B. Doyle et al.; Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout; Jun. 2003; Symposium on VLSI Technology Digest of Technical Papers; pp. 133-134; abstract. H. Takato et al.; High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs; 1988...
Threshold voltage (with and without body bias) for heterostructure pMOSFET is analytically explored as a function of applied bias for Si-SixGe1-x material system in presence of band-to-band tunneling. Threshold voltage for given device structure is calculated in the light of body effect for diff...