时序驱动(Timing-Driven)成品。一套新开发的自动化保持时间消除器(Hold Time Eliminator)以及路由器中的改良式延迟预测器, … blog.nownews.com|基于12个网页 2. 时间驱动技术 三、阿凡提的布局与绕线因为在时间驱动技术(Timing-driven)上的优势,继续扩大其市场份额,到二○○一年与凯登斯大致各占市场 … ...
网络释义 1. 时序驱动设计 材料科学专业英语词汇... ... timing data 时序资料timing driven design时序驱动设计timing driven layout 时序驱动配置 ... www.foodmate.net|基于16个网页
In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing...
履行timing-driven汇编 翻译结果5复制译文编辑译文朗读译文返回顶部 执行时间被驾驶的编辑 相关内容 a注意他的行动 Pays attention to his motion[translate] a老板让我通知你尽快解决这个问题 Boss lets me inform you to solve this problem as soon as possible[translate] ...
The timing-driven maze routing problem is then to find paths which exhibit low resistance-capacitance (RC) delay or achieve a tradeoff between RC delay and total capacitance. An easy-to-implement labeling algorithm is presented to solve the problem along with effective speedup enhancements to the ...
In this paper, we examine the emerging area of timing-driven hardware-software codesign. This area builds upon advances in embedded system design and real-time computing to drive the system design process. Timing driven codesign techniques are particularly relevant to the design of on-chip microelec...
We study the problem of dividing a given circuit into sub-circuits under a set of capacity and timing con-straints. A timing-driven bipartitioning technique based on an iterative quadratic programming formula-tion is presented. In contrast with move-based partitioning algorithms, the mathematical pr...
Given a set of connecting nodes in a signal net on different layers for 3D ICs, based on the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree. Compared with a spanni...
Timing-driven placement has been studied extensively over the last two decades. The drive for new methods in timing-driven placement to maximize circuit performance is from multiple facets due to the technology scaling and integration: (1) growing interconnect versus gate delay ratios, (2) higher ...
;mERROR:Place:1136 - This design contains a global buffer instance,ERROR:Pack:1654 - Thetiming-drivenplacementphaseencounteredanerror. 尼克wo2019-07-24 12:11:54 放置错误:1205,1136,1654使用时钟向导生成PLL时钟 ; CLOCK_DEDICATED_ROUTE = FALSE; >ERROR:Pack:1654 - Thetiming-drivenplacementphaseencoun...