A parallel algorithm for timing-driven globalrouting for standard cells. Zhaoyun, X,P Banerjee. Proceedings of1998International Conference onParallel Processing . 1998Xhaoyun Xing, et al., " A Parallel Algorithm for Timing-driven Global Routing for Standard Cells ", International Conference on ...
Timing-Driven Global Routing with Efficient Buffer Insertion*This work was supported in part by the NSFC under Grant No.60373012, the SRFDP of China under ... Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, ...
In this paper, we propose an efficient timing-driven global router, TIGER, for gate array and standard cell layout design. Unlike other conventional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to minimize the maximum chan...
Jun Gu, “A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design,” Design Automation Conference, 2004... J Xu,X Hong,J Tong,... - 《Integration the Vlsi Journal》 被引量: 23发表: 2006年 A coupling and crosstalk-considered timing-driven...
This paper presents a timing-driven global routing algorithm along with consideration of coupling effects and crosstalk avoidance. Our work differs from the existing ones in that we design a global routing “framework” which performs well in terms of routablity, timing, and also facilitates the ...
This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturally captures blockages, limited routing and wire-sizing resources, layer assignment, etc. Each edge in the multigraph is annota...
关键词: field programmable gate arrays network routing MCNC benchmark circuits TMRouter area-efficient timing-driven routing algorithm global routing algorithm negotiated congestion-delay algorithm scalable FPGA time-multiplexed interconnects time-sharing ...
New placement and global routing algorithms for standard cell layouts The placement algorithm, called the hierarchical clustering with min-cut exchange (HCME), is effective at avoiding being trapped in local optimum solutions... Edahiro,Yoshimura - IEEE Design Automation Conference 被引量: 37发表: ...
Performance-driven global routing for cell based ICs This problem is formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics... J Cong,AB Kahng,G Robins,... - IEEE 被引量: 82发表: 1991年 Performance and Th...
We propose timing-driven test point insertion methods for a full-scan based BIST scheme and for a partial-scan based BIST scheme, where the global flip-flo... KT Cheng,CJ Lin,EE Engineer - International Test Conference : Driving Down the Cost of Test: International Test Conference Washington...