The next inclusion in the industrial ASIC design flow is going to be automatic timing exception generation (ATEG). The current manual and reactive approach of identifying timing exceptions and doing timing closure through iterations will be addressed With ATEG tools able to make the design more ...
In Top-Down Digital VLSI Design, 2015 4.4.5 Timing constraints A timing constraint is a user-defined target for some timing quantity that the final circuit must meet. Fig.4.21 illustrates a common situation where the propagation delay through a circuit has been bounded from above. The concept ...