Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuitsimplemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterizationof the setup and hold times of the latches and flip-flops in the cell library. ...
It is known that Backward-Data-Direction (BDD) clocking is one of methods to guarantee the hold timing constraint. BDD clocking is a relative order relations between the arrivals of control signals at a pair of registers. In this paper, in addition to BDD clocking, we introduce Forward-Data...