TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT/RTC_REFIN 54 U1A STM32H750VB PC0/OTG_HS_ULPI_STP/EVENTOUT/ADC123_IN10 15 PC1/ETH_MDC/EVENTOUT/ADC123_IN11 16 PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT/ADC123_IN12 17 PC3/SPI2_MOSI/I2S2_SD/OTG_HS...
Pxy_C pins DDD Ethernet MII mode is not available on packages with PC2_C/PC3_C pins A A A HASH input data may be corrupted when DMA is used AAA LSE crystal oscillator may be disturbed by transitions on PC13 NNN Inaccurate LSE frequency in oscillator bypass mod...
( FIFO I M M RNG 1 ADC1 R FMC_signals 0 0 B Up to 20 analog inputs 0 0 H T 2 2 ( ( HASH A common to ADC1 2 CHROM-ART A 4 2 ADC2 FIFO M- Quad-SPI B B (DMA2D) S H H 3DES/AES AHB/APB A A U B CLK, CS,D[7:0] I LCD_R[7:0], LCD_G[7:0], LCD-TFT ...
PC2 PC3 VDD N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13 T...
ADC123_IN10 TIM1_CH1 PA8 D5 6 2 A1 PF8 ADC3_IN7 - PK1 D4 5 CN7 analog 3(1) 4(1) 5(1) A2 PA0_C ADC12_IN0 TIM3_CH1 A3 PA1_C ADC12_IN1 - ADC3_IN0 A4 PC2_C or PD13 (PC2) or I2C1_SDA USART1_TX (PD13) PA6 PG3 PB6 D3 4 D2 3 CN6 digital D1 2 ADC3_...