C PC0/OTG_HS_ULPI_STP/EVENTOUTADC123_IN1016C-PA10100kGND NLPCX20 PC1/ETH_MDC/EVENTOUT/ADC123_IN11NLPCX213V3 17C- PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT/ADC123_IN12NLPCX22 18C- PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT/ADC123...
PC2_C.Signal=SharedAnalog_PC2 PC3.GPIOParameters=GPIO_Label PC3.GPIO_Label=MII_TX_CLK PC3.Locked=true PC3.Mode=MII PC3.Signal=ETH_TX_CLK PC3_C.Locked=true PC3_C.Mode=IN1-Differential PC3_C.Signal=ADC3_INP1 PC4.GPIOParameters=GPIO_Label PC4.GPIO_Label=MII_RXD0 PC4...
TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT/RTC_REFIN 54 U1A STM32H750VB PC0/OTG_HS_ULPI_STP/EVENTOUT/ADC123_IN10 15 PC1/ETH_MDC/EVENTOUT/ADC123_IN11 16 PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT/ADC123_IN12 17 PC3/SPI2_MOSI/I2S2_SD/OTG_HS...
( FIFO I M M RNG 1 ADC1 R FMC_signals 0 0 B Up to 20 analog inputs 0 0 H T 2 2 ( ( HASH A common to ADC1 2 CHROM-ART A 4 2 ADC2 FIFO M- Quad-SPI B B (DMA2D) S H H 3DES/AES AHB/APB A A U B CLK, CS,D[7:0] I LCD_R[7:0], LCD_G[7:0], LCD-TFT ...
Pxy_C pins DDD Ethernet MII mode is not available on packages with PC2_C/PC3_C pins A A A HASH input data may be corrupted when DMA is used AAA LSE crystal oscillator may be disturbed by transitions on PC13 NNN Inaccurate LSE frequency in oscillator bypass mod...
(1) 4(1) 5(1) A2 PA0_C ADC12_IN0 TIM3_CH1 A3 PA1_C ADC12_IN1 - ADC3_IN0 A4 PC2_C or PD13 (PC2) or I2C1_SDA USART1_TX (PD13) PA6 PG3 PB6 D3 4 D2 3 CN6 digital D1 2 ADC3_IN1 6(1) A5 PC3_C or PD12 (PC3) or I2C1_SCL USART1_RX (PD12) PB7 D0 1...