This cleared a few errors, however, the SMD Pin to SMD Pin DRC errors remain with P><P indicators in between ULN2003 pads as well as capacitor and resistors pads on the associated nets. I deleted partial traces to the chips and rerouted these nets. This cleared the ...
Problem I'm having is that if I turn off "Same Net Spacing - Thru Via To SMD Pin", both of the below are allowed, but I want the first one to give me a DRC error. Via, pad and shape are all on the same net here. /F
我设置的区域规则是5mil但是bga区域老显示pv错误，显示SMD Pin to Thru Via Same Net Spacing 8mil ...
Route Keepout Spacing 只是说这一区域不能有线，只要不在这个区域里面就不会报DRC的，具体设置如下所示
所以我們可以把SameNetSpacing:ShapetoThruPin改成15mils,ShapetoSMDPin則不變5mils 在UpdatetoSmooth後,可以看到在ThruPin的部份,對Shape的間距拉大到15mils 範例二. 也可以將SameNetSpacing運用在DelayTune上: 假設某一個net有設定走線的長度限制,我們會利用DelayTune來做延長繞線長度的操作,但又希...
But I cannot seem to see these updated footprints on the board. For instance, one of my package footprints had 16 pins, i removed pins 1 and 4 and saved it the package symbol. When I go back to the board to update the place the same package it is still the 16 pin version. And ...
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Hello, I route a board on Cadence 14.0 and have an unknown problem. Each time I try to connect 2 pins of a same net, I have 2 DRC errors : Line to SMD Pin Spacing. More over, when I connect these 2 pins, it is not automaticaly directed to the cent...
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