Line to SMD Pin Spacing 走线与SMD元件脚太近 可是这些走线是与该引脚相连的 设置一个规则区域就可以解决此问题, 谢谢,能否具体点,这规则如何设置 呵呵不好意思,没有明白 器件管脚太近,连接这个管脚的线到和这个管脚相邻的管脚的距离小于了你规则里面设的最小间距,所有报错,我一般是画一个区域规则。 你规则设置有问题吧 应该是你的走线和焊盘不在一...
SMD Pin to >>, etc...) using Spacing CSet. When I started routing the OUTPUT[1..6] nets, various DRC errors popped up at the ULN2003 chips. I realized my mistake by having 50mils clearance for all OUTPUT[1..6] nets. I then removed ...
Hello, I route a board on Cadence 14.0 and have an unknown problem. Each time I try to connect 2 pins of a same net, I have 2 DRC errors : Line to SMD Pin Spacing
Problem I'm having is that if I turn off "Same Net Spacing - Thru Via To SMD Pin", both of the below are allowed, but I want the first one to give me a DRC error. Via, pad and shape are all on the same net here. /F