set_clock_gating_style -sequential_cellnone-positive_edge_logic {or} 2) {integrated}用于表明使用上升沿触发的ICG单元。 如下图所示,该ICG单元就是一个pre-conctrolled positive-edge triggered clock gating latch。 -negative_edge_logic {cell_list | integrated [active_low_enable] [invert_gclk]} 1) ...