Shah M . Efficient scan2based BIS T scheme for low power testing of VL SI chip s [ C] ΠΠProceedings of International Sympo sium on Low Power Elect ronics and Design , Tegernsee , 2006 : 3762381Malav Shah, " Efficient Scan-Based BIST Scheme for Low Power Testing of VLSI Chips", ...
Compact Test Sequences for Scan-Based Sequential Circuits (Special Section on VLSI Design and CAD Algorithms) Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many tes... Higuchi,Hiroyuki,Hamaguchi,....
Low-Energy Pattern Generator for Random Testing A new built-in self-test (BIST) scheme for scan-based circuits is proposed for reducing energy consumption during testing. In a random testing environment,... B Bhattacharya,S Seth,S Zhang 被引量: 0发表: 2009年 Improvement of the connection set...
According to the characteristic of the networks that are AC-coupled,differential,or both based on boundary-scan,the testing method basing on IEEE1149.6 is provided,and the capability of noise rejection in the AC test mode is analyzed. The testing results show that AC test mode can realize the...
Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional se... A Apostolakis,M Psarakis,D Gizopoulos,... - European Test Symposium 被引量: 15发表: 2009年 A model for predicting overall survival in men...
A low-cost solution for protecting IPs against scan-based side-channel attacks Scan designs used for testing also provide an easily accessible port for hacking. In this paper, we present a new low-cost secure scan design that is effec... J Lee,M Tebranipoor,J Plusquellic - IEEE Vlsi ...
Scan chain based test has been a common and useful method for testing VLSI designs due to its high controllability and observability. However scan chains h... G Sengar,D Mukhopadhayay,DR Chowdhury - International Conference on Advanced Computing & Communications 被引量: 30发表: 2007年 New scan...
Scan chain design for shift power reduction in scan-based testing Test power of VLSI systems has become a challenging issue nowadays. The scan shift power dom- inates the average test power and restricts clock frequency o... LI Jia,HU Yu,LI Xiaowei - 《Science China(Information Sciences)》...
摘要 Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling techni... 出版源 IEEE , 2008 关键词 boundary scan testing / integrated circuit testing / power consumption / LSC-filling technique / X-fllling technique / boundary scan ...
TestingScan chainThe power consumption of IC during test mode is higher than its normal mode. This brings the power asone of the major design constraints for today's low power design technologies. In normal scan based testcircuits most of the power consumed due to the switching activity of ...