A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCSdifferential nonlinearity (DNL)integral nonlinearity (INL)successive approximation register (SAR) analog-to-digital converter (ADC)Successive approximation register (SAR) analog-to-digital converters (ADCs)...
图1所示为一种用于上板取样(topplatesampling)方式的SARADC电路,其中上板取样开关的非理想特性对于较高分辨率模数转换器而言具有一定的限制性。当CDAC电容权重和电容值有误差时,SARADC的模拟数字对应关系就会出现线性度失真。 发明内容 鉴于上述内容,有必要提供一种SAR模数转换器,本申请实施例可以将数字权重对应到真实的...
The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9W and ENOB of 7.41-bit. 展开 关键词: successive-approximation-register(SAR) ADC top plate sampling bootstrap switch low-voltage ...
Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator...
Fig. 4(a) shows the operation of a SAR ADC with a 12-bit DAC, C11–C0. In the sampling phase, the input signal is sampled on the DAC top plate and all the digital codes reset. In the conversion phase, the DAC cells are switched sequentially based on a binary search algorithm and...
topplateofDACcapacitorarray.Finally,theNoise-shapingSARADCdesigned achieveshighprecision(SNDR,90dB)andlowpowerconsumption(µWorder). Basedon0.18µm1P4MCMOStechnology,theoveralllayoutareaofNoise- shapingSARADCis793µm×338µm.Undertheconditionsofsupplyvoltageof 1.8V,samplingclockfrequencyof2MHzandove...
一种10位200 kSs 65 nm CMOS SAR ADC IP核 星级: 6 页 A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator 星级: 8 页 A 10-bit 50 MSs SAR ADC in 65 nm CMOS with on-chip reference voltage buffer 星级: 11 页 A 10-bit 300-MSs asynchronous...
toachievelowareaandlesscapacitiveloadandthusenhancespowerefficiency. Top-platesamplingisutilizedintheDACtoreducethenumberofswitches.Inpost-layoutsimulation whichincludestheentirepadframeandassociatedparasitics,theADCachievesanENOBof9.25bitsata supplyvoltageof1.2V,typicalprocesscornerandsamplingfrequencyof50MS/sfor...
Furthermore, we introduce a full-scale matching residue amplification technique for the prototype pipelined-SAR ADC to utilize the top-plate input sampling for the first-stage SAR ADC, resulting in faster and lower power conversion. The prototype ADC demonstrates the robustness of our dynamically ...
The ADC sampling network, which includes the 16-bit DAC and the 3-bit flash blocks other than the flash comparators, operates at 3.3 V to accommodate traditional precision applications, the rest of the circuits all operate under 1.2 V supply. The digital engine includes bit weight calibratio...