随着数字终端的不断发展,各类产品对模数转换器(Analog-to-Digital Converter,ADC)的速度、精度、功耗等性能要求不断提升,传统单一架构ADC难以满足当前需求。而混合结构的ADC结合了不同架构的优点,提高了ADC的性能,成为研究的热点。作为逐次逼近(Successive Approximation Re
acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications ATE GENERAL DESCRIPTION The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. ...
治精微 - ADC,精密放大器,低功耗精密电压基准源,精密运算放大器,OP AMP,高端信号链,DIFFERENCE AMPLIFIER,精密数据转换器,精密数模转换器,连续信号处理放大器,INSTRUMENTATION AMPLIFIER,精密信号源,高压多路复用器,MUX模数转换器,模拟芯片,差动放大器,精密模数转换器,放大器,温度传感器,DIFFERENCE AMPLIFIER,串联型电压基...
2.5 MSPS PulSAR®successive-approximation ADC, combined with an autorangingAD8253iCMOS®programmable gain instrumentation amplifier (PGA) front end. With gain that changes automatically based on analog input value, it uses oversampling and digital processing to increase the dynamic range of the syste...
2.7.2 Current Input Signal Conditioning The current signal-conditioning circuit includes a CT with a burden that can be configured, an instrumentation amplifier or precision amplifier to scale the CT output to the ADC range, and a jumper to choose between instrumentation or precision amplifier ...
The LTC®2387-16 is a low noise, high speed, 16-bit 15Msps successive approximation register (SAR) ADC ideally suited for a wide range of applications. The combination of excellent linearity and wide dynamic range makes the LTC2387-16 ideal for high speed imaging and instrumentation applicatio...
18-Bit 1.6Msps SAR ADC 101dB SNR Up to 5V 0V Up to 5V 2.5V 2.5V to 5V IN+ VDD VREF LTC2379-18 SPI I/O IN– GND 0V Unrivaled Performance at Only 18mW The LTC®2379-18 leads a pin-compatible family of no-latency SAR ADCs featuring unrivaled 101dB SNR at 18-bits and 96dB...
The SAR ADC uses a pseudo-differential RC DAC and a split capacitor array to reduce power consumption and chip area. To improve the sampling rate and accuracy of the column ADC, a dynamic comparator consisting of a two-stage preamplifier and a latch, as well as the output offset storage ...
Design of 1.2V, 6-bit SAR ADC is implemented using cadence at 90nm CMOS process, which consumes 802.6W.Meghana KulkarniMuttappa ShingadiG.H. KulkarniInternational Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy...
Figure 1 shows a typical amplifier, single-pole RC filter, and ADC. The ADC input presents a switched-cap load to the driving circuitry. Its 10-MHz input bandwidth means that low-noise is needed over a wide bandwidth to get a good signal-to-noise ratio (SNR). The RC network limits th...