and the second reservoir capacitor on the chip, the first reservoir capacitor discharged or configured not to deliver charge to the SAR ADC; the second reservoir capacitor is charged; and inserting the first and second reservoir capacitors in the same manner as during a normal conversion sequence....
”All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 10, pp. 2355-2365, Oct. 2011.
CALIBRATION TECHNIQUES FOR SAR ADCS WITH ON-CHIP RESERVOIR CAPACITORS 机译:带有片上储层电容器的SAR ADC的校准技术 摘要 When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error ...
Low-power high-performance SAR ADC design with digital calibration techniques This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct ... W Liu 被引量: 6发表: 2011年 A 12 bit 40 MSPS SAR ADC with...
A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this wo...
Circuit design techniques that help enable this ADC are presented in Section III, including optimal LSB repeats, one reservoir-capacitor per bit-capacitor DAC, calibration with existing LSB capacitors, and statistical residue measurement (SRM). Experimental results are shown in Section IV followed ...
) 工程硕士学位论文题目 国防科学技术大学研究生院 DesignandImplentionofa12bitSARADC withdigitalcalibration Candidate:changliping Advisor:lijinwen Athesis Submittedinpartialfulfillmentoftherequirements fortheprofessionaldegreeofMasterofEngineering inIntregratedCircuitDesign GraduateSchoolofNationalUniversityofDefense...
The implementation of the redundant in a 10-b SAR ADC is like this: Reference [1]:Liu et al. - 2010 - A 10-bit 50-MSs SAR ADC with a monotonic capacitor switching procedure. [2]:Yoshioka et al. - 2010 - A 10-b 50-MSs 820-μW SAR ADC with on-chip digital calibration ...
一种应用于SAR ADC的非二进制单位电容C-αC DAC及其校准方法.pdf,本发明涉及一种应用于SARADC的非二进制单位电容C‑αCDAC及其校准方法,属模拟集成电路技术领域。电路包括采样开关、电容阵列、比较器、逐次逼近控制模块和数字校准模块,其中,比较器输入端一侧连接有电容
高精度逐次逼近型模数转换器(SARADC)的研究与设计学校代码10701分类号TN4学号17111212805密级公开西安电子科技大学硕士学位论文作者姓名:***:软件工程学位类别:工程硕士学校导师姓名**称:柴常春教授企业导师姓名**称:徐峰高工学院:微电子学院提交日期:2020年4月StudyandDesignofHigh-PrecisionSuccessiveApproximationRegisterAnal...