delay effect (GERDE), is studied for short-channel MOSFET's. A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a si
Keywords:copperinterconnect;capacitance;low——permittivitydielectrics;reliability;RCdelay 引言 IC的集成度和性能的提高激励着40多年来的 半导体工业和由此产生的信息革命。迄今为止, 利用器件按比例和/或芯片尺寸增加方法,在集成 度和性能方面的改进周期达到了摩尔定律预期的 变化。对经典的晶体管来说,器件性能的改进...
DepartmentJadavDepartmentMunishDepartmentVashishthDepartmentRajeevanDepartmentChandelDepartmentInformaworldInternational Journal of Modelling & SimulationS. Jadav, M. Vashishth, and R. Chandel, "RLC equivalent RC delay model for global VLSI interconnect in current mode signaling," Int. J. Model. Simul., ...
关键词:铜互莲线;电容;低介电常数;可靠性;Rc延迟 405.97 中图分类号:TN 文献标识码:A RC of Interco衄ectioninUSLI DelayTechnologyCopper XUAN Jiu一】【ia,LUZhen—jun,UZhi—guo Universty 100022,China) (Be玎i“g of‘rechn0109yBe妇i“g Abst】.act:neI面皿ationRevoludonand eraofsilicon enabⅡ...
Rubinstein, “Signal delay in RC tree networks.” Proceedings of Caltech Conference on VLSI, pp. 269–283, January 1981. Google Scholar J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Transactions on Computer-Aided Design, CAD-2(3), ...
This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negat...
The clamp transistor would be automatically turned off after the fixed time delay in the turn-off path even if it is falsely triggered. The proposed circuit has simpler circuit structure while maintaining long enough turn-on time of clamp transistor, thus providing higher ESD protection robustness....
drivingeachindividualinterconnecttreewhilemaintainingcomputationalsimplicityforuseintheautomatedtiming analysisofcomplexVLSIcircuits. KeyWords:RCtrees,interconnectimpedance,rampinputresponse I.Introduction RCtreesarecommonstructuresindigitalintegrated circuitswithinboththecontrolandthedataportions ...
In reality,the oscillation period equals t=t 0 +t INV , where t INV represents the propagation delaythrough the inverting gain stages. Because the local supply voltage tracks thethreshold of the NMOS and PMOS devices, the t INV through the inverting elements is almost constant over temperature...
2) coupling RC interconnect 耦合RC互连 1. An approach for analyzing coupling RC interconnect delay based on “effective capacitance” is presented. 基于“有效电容”的概念提出了一种分析两相邻耦合RC互连延时的方法。3) interconnect [英][,ɪntəkə'nekt] [美]['ɪntɚkə'nɛkt] ...