A pseudo-NMOS or PMOS inverter comprises a first p-type or n-type field effect transistor (FET) (502, 504), and a second n-type or p-type FET (506, 508) having second gate, source, and drain electrodes. The second gate electrode forms an input to the inverter, and the second ...
The delay element (210) further comprises a node (310) comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage (112) is included for applying a biasing voltage to the first and second control inputs to...
The proposed design consists of five inverter stages, and pseudo-NMOS topology is used to replace the current sourcing PMOS blocks, thereby reducing power consumption to 155.7 渭W for fundamental frequency of 1.8 GHz. The simulation results depict that the proposed CSVCO has better phase noise ...
Figure 6shows a block diagram of the proposed Pseudo-NMOS comparator-based programmable divide-by-N clock frequency divider, which comprises a new count detector, an inverter, and a control block. The control block includes a 5-bit synchronous UP counter and a reset logic. This clock divider ...