A pseudo-NMOS or PMOS inverter comprises a first p-type or n-type field effect transistor (FET) (502, 504), and a second n-type or p-type FET (506, 508) having second gate, source, and drain electrodes. The second gate electrode forms an input to the inverter, and the second ...
A pseudo-NMOS or PMOS inverter comprises a first p-type or n-type field effect transistor (FET) (502, 504), and a second n-type or p-type FET (506, 508) having second gate, source, and drain electrodes. The second gate electrode forms an input to the inverter, and the second drai...
This paper presents an NMOS pseudo-digital low-dropout (PD-LDO) regulator that supports low-voltage operation by eliminating the amplifier of an analog LDO... J Tang,C Zhan,G Wang,... - IEEE 被引量: 0发表: 2018年 An Adaptive Digitally Tuned Flash-based LDO with Reduced Hardware for Sen...
NMOS access transistors 33 and 35. A second port is controlled by a word line 37 and bit lines 39 and 41. Word line 37 controls the potential on the gates of two NMOS access transistors 43 and 45. As shown, access transistors 33 and 35 of the first port are arranged at opposite ...
The proposed design consists of five inverter stages, and pseudo-NMOS topology is used to replace the current sourcing PMOS blocks, thereby reducing power consumption to 155.7 渭W for fundamental frequency of 1.8 GHz. The simulation results depict that the proposed CSVCO has better phase noise ...
Another solution is illustrated for the pseudo-dynamic latch circuit is illustrated in FIG.5. For purposes of illustration, only the pull down paths510and520of data signals D1and D2are illustrated. As can be seen from a comparison of FIG.1and FIG. 5, an additional NMOS transistor560has be...
output node;a second NMOS transistor having a gate receiving an output signal of the third inverter, a drain connected to a source of the first NMOS transistor, and a source connected to the second voltage; anda third NMOS transistor having a gate receiving an output signal of the falling ...
The delay element (210) further comprises a node (310) comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage (112) is included for applying a biasing voltage to the first and second control inputs to...
Figure 6shows a block diagram of the proposed Pseudo-NMOS comparator-based programmable divide-by-N clock frequency divider, which comprises a new count detector, an inverter, and a control block. The control block includes a 5-bit synchronous UP counter and a reset logic. This clock divider ...