see "http://www.eda.org/sv-bc/hm/att-0595/01-port_connection_rules.pdf" for Systemverilog port connection rules. Kr, Florian --- Quote End --- Thank you for your response. I will keep it in mind to always use .sv extension for compatibility with all tools. I noticed that...
The following table lists the supported port types. Table 1. Supported Port Types VHDL 1 Verilog/SV 2 IN INPUT OUT OUTPUT INOUT INOUT Buffer and linkage ports of VHDL are not supported. Connection to bi-directional pass switches in Verilog are not suppor
As a matter of fact, it is required to mix SystemVerilog .* or DAC 2008 Rev 1.1 3 SystemVerilog Implicit Ports Enhancements Accelerate System Design & Verification .name implicit port connections with named ports if rules 3 - 6 apply (see below). The following rules apply if the individual...
The standard doesn't give explicit rules for mismatched port widths, so is open to interpretation (that's why Icarus outputs warning messages, telling you what it is going to do). I think the key paragraph in the standard is: Each port connection shall be a continuous assignment of source...