The two types of port connections shall not be mixed (in Verilog) in a single declaration. For a Verilog module that does not have any port, you still need to write the parentheses when instantiating it. As to what to connect to the port, from Verilog, it can be a register or net i...
I'd not know that synthesis supported this in VHDL. As it is, I only use VHDL for vendor provided IP - the bulk of all my designs are written in verilog. And since verilog couldn't accept such a construct across the mixed-language boundary, none of our provided IP could use it, and...