在always@(r)，r是在信号列表里，但是r并不参与运动。而在always@(r)里，出现想赋值右边的信号sw, cnt，都不在信号敏感列表里。所以从仿真的角度看，always@(r)这句话是完全多余的。因此，led1也就不会被赋值了。
To investigate this further, I opened the SDF file and looked for the cell definition of a failing flipflop: Code: (CELL (CELLTYPE "DFQRM2RA") (INSTANCE duv.reg) (DELAY (ABSOLUTE (PORT RB (::0.0)) (PORT CK (::0.0)) (PORT D (::0.0)) (...
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Do you see anything wrong with this power supply and ground definition? Could it effect the convergence? Regarding the tolerance. I did try to loosen the voltage, current and the reltol tolerances and it didn't help the convergence.
1) 自上而下:在主原理图图纸下,通过“Design》Create sheet from symbol”、“Design》Create HDL file from symbol》Create VHDL file from symbol”与“Design》Create HDL file from symbol》Create Verilog file from symbol ”等命令创建子图纸、底层VHDL文件和底层Verilog文件。