生成IP后，打开官方例程，路径位于生成IP工程目录下的example_design。 检查并根据开发板配置信号引脚，如ref_led/pclk_led、smlh_link_up/rdlh_link_up等，这些信号有助于PCIE链路测试。 完成引脚调整后，生成bitstream以供下载。 驱动紫光PCIE：实战应用 将FPGA固件烧录到开发板，插入主机PC...
…_ops" Revert this commit as it wasn't reliably work as expected by massive test. The problem is clear now that cxpl_debug_info from DWC core is missing rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up isn't enough. Quoted from DWC databook, section 8.2.3 AXI ...
if((val&(RDLH_LINKUP|SMLH_LINKUP))==0x30000) return1; } return0; } staticvoidrk_pcie_enable_debug(structrk_pcie*rk_pcie) { if(!IS_ENABLED(CONFIG_DEBUG_FS)) Expand DownExpand Up@@ -1601,7 +1583,6 @@ MODULE_DEVICE_TABLE(of, rk_pcie_of_match); ...
[ 17] [ RW] rdlh_link_up = 0x1 [ 16] [ RW] smlh_link_up = 0x1 [10:08] [ RW] l1sub_state = 0x3 [05:00] [ RW] smlh_ltssm_state = 0x13 [0x0014] 0x00000133 CLIENT_INTR_STATUS_PMC [ 8] [ W1C] pm_dstate_update_int = 0x1 [ 7] [ W1C] linkst_out_l0s_int ...