其中ref_led/pclk_led可以表明主机的PCIE接口时钟能够给到FPGA硬核,smlh_link_up/rdlh_link_up可以表明主机与FPGA硬核能够链接成功,link_up后主机内核程序可以读到PCIE的配置空间信息,进而给FPGA的PCIE分配PCIE总线域空间(bar基地址也在初始化给到PCIE硬核配置空间)。 (7)修改好相关信号的引脚分配后,就可以生成bitst...
1. For multiple VC configurations, only VC0 should be enabled before the link is up. Other VCs should be enabled after rdlh_link_up is asserted. 2. The application logic must not generate any MEM or I/O requests until the host software has enabled the BME. The Synopsys controller does ...
生成IP后，打开官方例程，路径位于生成IP工程目录下的example_design。 检查并根据开发板配置信号引脚，如ref_led/pclk_led、smlh_link_up/rdlh_link_up等，这些信号有助于PCIE链路测试。 完成引脚调整后，生成bitstream以供下载。 驱动紫光PCIE：实战应用 将FPGA固件烧录到开发板，插入主机PC...
若PCIe 控制器与对端设备之间的连接未建立,不可向对端设备发起任何PCIe 事务。 软件通过查询系统控制寄存器PERICTRL39[pcie0_rdlh_link_up]可以确定PCIe0 控制器 是否已与对端设备建立连接。 软件通过查询系统控制寄存器PERICTRL40[pcie1_rdlh_link_up]可以确定PCIe1 控制器 是否已与对端设备建立连接。 请参考...
val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); +#if 0 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); ...
…_ops" Revert this commit as it wasn't reliably work as expected by massive test. The problem is clear now that cxpl_debug_info from DWC core is missing rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up isn't enough. Quoted from DWC databook, section 8.2.3 AXI ...
if((val&(RDLH_LINKUP|SMLH_LINKUP))==0x30000) return1; } return0; } staticvoidrk_pcie_enable_debug(structrk_pcie*rk_pcie) { if(!IS_ENABLED(CONFIG_DEBUG_FS)) Expand DownExpand Up@@ -1601,7 +1583,6 @@ MODULE_DEVICE_TABLE(of, rk_pcie_of_match); ...
[ 17] [ RW] rdlh_link_up = 0x1 [ 16] [ RW] smlh_link_up = 0x1 [10:08] [ RW] l1sub_state = 0x3 [05:00] [ RW] smlh_ltssm_state = 0x13 [0x0014] 0x00000133 CLIENT_INTR_STATUS_PMC [ 8] [ W1C] pm_dstate_update_int = 0x1 [ 7] [ W1C] linkst_out_l0s_int ...
Subsystem ID :同 h class Code 用于区分设备的一般功能,分为3种类型: Base Class :概括地标识器件所执行功能的类型 Class Cede [3 Vse dess Code Lcokup Assi et axit Base 71ass Menu Base Cliss Sub Class Interface Menn Sab-Cl ms Tnt Clftzc Codo (Max): Simple conmon;cation controllers ▼ Ran...
dev_info(pp->dev,"Link up\n");return0; } 开发者ID:qkdang,项目名称:m462,代码行数:28,代码来源:pci-exynos.c 示例2: exynos_pcie_power_off_phy ▲点赞 5▼ staticvoidexynos_pcie_power_off_phy(struct pcie_port *pp){ u32 val;structexynos_pcie*exynos_pcie=to_exynos_pcie(pp);val = ...