The method further includes forming a layer of photoresist and then patterning the layer of photoresist to protect a middle portion of the polysilicon layer of the non-silicided poly resistor stacks , etching the exposed portions of the dielectric capping layer , and removing the patterned ...
and etch processes required by the method of the present invention. It will be understood that the gate electrode material may include a silicide or polycide composition. The chemistry and fabrication techniques employed in the method of the present invention are known in the art and constitute co...
As discussed above, the semiconductor layers may be formed using polysilicon or an amorphous silicon. The conductors may be a highly doped silicon or a metal, metal alloy, silicide or combinations thereof. The dielectric fill in the spaces between the pillars is also used, as discussed for the...
The method further includes forming a layer of photoresist 180 and then patterning the layer of photoresist 180 to protect a middle portion of the polysilicon layer 100 of the non-silicided poly resistor stacks 30, etching the exposed portions of the dielectric capping layer 170, and removing ...
To reduce the required memory area a 3T memory cell is proposed comprising a bridge of two bridge transistors (MN MN), preferably NMOS transistors, a read transistor, preferably an PMOS transistor, and a silicided polysilicium fuse resistor (R). The read transistors enable the use of a ...
Baldi et al., “A Scalable Single Poly Eeprom Cell for Embedded Memory Applications,” pp. 1-4, Fig. 1, Sep. 1, 1997. Cao, Ke, “Design for Manufacturing (Dfm) in Submicron Vlsi Design,” Aug. 1, 2007. Capodieci, Luigi, “From Optical Proximity Correction to Lithography-Driven ...
In a case where tungsten silicide (WSi) is used for the control gate34, it is considered that abnormal oxidation of WSi will occur due to the annealing process effected in the oxidation atmosphere. The abnormal oxidation of WSi tends to occur in a portion where the gate length of the cell...
8. The MOSFET structure of claim 1, wherein the junction depth of said first and second resistor wells is variable. 9. The MOSFET structure of claim 8, wherein a silicide blocking mask is deposited above said first and second resistor wells thereby inhibiting the formation of silicide and de...
22. The semiconductor structure of claim 15 wherein said gate conductor comprises polySi, SiGe, an elemental metal, an alloy of an elemental metal or a silicide of an elemental metal. 23. The semiconductor structure of claim 15 further comprising a Si-containing material within each of the ...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising materi