and etch processes required by the method of the present invention. It will be understood that the gate electrode material may include a silicide or polycide composition. The chemistry and fabrication techniques employed in the method of the present invention are known in the art and constitute co...
The conductive layers114,123,128may be formed using any of numerous well-known thin-film deposition processes such as sputtering. A refractory metal may be used, or a silicide of a refractory metal may be used. Other alternatives include aluminum, copper, or heavily doped silicon. In one embo...
8. The MOSFET structure of claim 1, wherein the junction depth of said first and second resistor wells is variable. 9. The MOSFET structure of claim 8, wherein a silicide blocking mask is deposited above said first and second resistor wells thereby inhibiting the formation of silicide and de...
1, wherein the gate electrode of each of the plurality of erasable and programmable memory cell transistors, the selection transistor, and the peripheral transistor is a stacked gate structure including a floating gate and a control gate, the control gate comprising a metal or a metal silicide....
Deng, Liang et al., “Coupling-aware Dummy Metal Insertion for Lithography,” p. 1, col. 2, Jan. 23, 2007. Devoivre et al., “Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC),” Jul. 12, 2002. Enbody, R. J., “Near-...
programming a polycide (i.e. polysilicon with silicide on top) fuse takes about 60 mA for 100 millisecond. The program current is so high that the shared pin or the nearby interlayer dielectric can be damaged. The area for a one-pad-one-fuse OTP cell is also very large, especially for...
22. The semiconductor structure of claim 15 wherein said gate conductor comprises polySi, SiGe, an elemental metal, an alloy of an elemental metal or a silicide of an elemental metal. 23. The semiconductor structure of claim 15 further comprising a Si-containing material within each of the ...
Examples include metals and compounds such as W, Ni, Mo, Pt, metal silicides, and the like. Examples of solid electrolytes materials are: TaO, GeSe or GeS. Other systems suitable for use as solid electrolyte cells are: Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W, and Ag/GeS/W, ...
John P.S. (Spokane, WASHINGTON, US) Claims: The invention claimed is: 1. A method of forming a non-volatile resistive oxide memory cell, comprising: forming a first conductive electrode of the memory cell as part of a substrate, the first conductive electrode comprising one or more ...
A typical silicided row line resistance per cell is 20 ohms. A typical source line capacitance per cell is 2 fF. A typical bitline capacitance per cell is 1.5 fF. And a typical row line capacitance per cell is 3 fF. Hence for the 8192×16384 array, the total bitline capacitance is...