9. The MOSFET structure of claim 8, wherein a silicide blocking mask is deposited above said first and second resistor wells thereby inhibiting the formation of silicide and deepening the junction depths of the first and second resistor wells. ...
6.The semiconductor device according to claim 1, further comprising an eighth diffusion layer whose conductivity type is the same as that of the sixth diffusion layer and which is used to form a MOSFET having a different conductivity type and formed in the non-silicide region of the second MOS...
[0011] A method of fabricating an integrated circuit having n-channel and p-channel transistors in a CMOS device is provided in accordance with the present invention. The method includes forming gate electrodes over n-type and p-type silicon regions that define isolated active areas of the devic...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising materi
The silicidation process can provide a fully silicided gate or a partially silicided gat including a top silicide layer and a bottom metal layer. Next, and as shown in FIG. 9A, a Si-containing material 28 such as polysilicon, single crystal single, amorphous silicon, and SiGe, is ...
In a preferred embodiment, pull-down device 525 is a resistor. On an integrated circuit, a resistor may be fabricated using many different techniques and from different devices. For example, a resistor may formed using polysilicon, undoped polysilicon, polysilicide, n-type diffusion, p-type ...