The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem ...
A transition has a delay of firing resulting in a random firing. At each timed transition t, one can associate a clock. When t is enabled, the clock is initialized with a value y; y is decremented with a constant speed and when its value is 0, t is fired. The delay of the firing...
Y Peng,L Xun - IEEE Computer Society Symposium on Vlsi: New Frontiers in Vlsi Design 被引量: 2发表: 2005年 Chapter 7 - Timing Optimization for Two-Terminal Interconnects This chapter describes a technique and an algorithm that decrease the delay of two-terminal interplane interconnects by optim...
consist of capacitively coupled three parts in stripline structure, a A/4 open T resonator, a 位/4 short-circuited line, and input and output lines. ... TH Duong,IS Kim - 《IEEE Microwave Theory & Techniques》 被引量: 104发表: 2009年 Delay and noise estimation of CMOS logic gates driv...
vTaskDelay( webSHORT_DELAY ); }#endifif( pxRxBuffer !=NULL) {/* Where is the data? */netbuf_data( pxRxBuffer, (void* ) &pcRxString, &usLength );/* Is this a GET? We don't handle anything else. */if((NULL!= pcRxString ) ...
This paper presents a new model for VLSI routing in the presence of obstacles, that transforms any routing instance from a geometric problem into a graph p... J Ganley,JP Cohoon - IEEE 被引量: 209发表: 1994年 Board-level multiterminal net routing for FPGA-based logic emulation F. Wong,...
A Real Delay Switching Activity Simulator based on Petri net Modeling Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consu... N Ranganathan,AK Murugavel - International Conference on Design Automatio...
VLSI 160-4094-00 MADE FOR TEKTRONIX CUSTOM IC 4 $75.00 NEW 160-4288-05 SEALED IN ANTI STATIC BAG /SITTING IN ANTISTATIC FOAM 4 $25.00 > 160-4384-05 SEALED IN ANTI STATIC BAG /SITTING IN ANTISTATIC FOAM 2 $25.00 > 160-4385-05 SEALED IN ANTI STATIC BAG /SITTING IN ANTISTATIC FOAM 2...
Sensitivity Analysis. I. INTRODUCTION It has been widely recognized that interconnect becomes a dominant factor in determining the overall performance and complexity for deep submicron VLSI circuits. The global wiring delay can easily be a factor of ten or hundred times of a logic gate delay, even...
delay path including inverting delay elements 702, 704, and 706 coupled in series between CLK 178 and the first input of NAND gate 714. Any odd number of inverting delay elements may be used. For an alternative embodiment, any combination of inverting and/or non-inverting delay elements may ...