The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem ...
A transition has a delay of firing resulting in a random firing. At each timed transition t, one can associate a clock. When t is enabled, the clock is initialized with a value y; y is decremented with a constant speed and when its value is 0, t is fired. The delay of the firing...
delayacct.h delayed_call.h dev_printk.h devcoredump.h devfreq-event.h devfreq.h devfreq_cooling.h device-mapper.h device.h device_cgroup.h devm-helpers.h devpts_fs.h dfl.h digsig.h dim.h dio.h dirent.h dlm.h dlm_plock.h dm-bufio.h dm-dirty-log.h dm-io.h ...
dominant factor in determining the overall performance and complexity for deep submicron VLSI circuits. The global wiring delay can easily be a factor of ten or hundred times of a logic gate delay, even with repeater insertion [1]. Since interconnect length is roughly determined by the placement...
The invention accurately determines propagation delay for a sawtooth pattern. Through measurement, the actual delays added per bend in the sawtooth pattern are determined and the values are then used
According to the character of codebook size and codeword dimension in low delay speech coding algorithm, a codebook design algorithm based on modified self... S Wu,Z Gang,X Zhang,... - IEEE 被引量: 11发表: 2008年 Quantitative properties of Kohonen's self‐organizing maps as adaptive vector...
Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours ... A Rajagopal,A Rajaram,R Damodaran,... - Proceedings of SPIE - The International Society for Optical Engineering 被引量: 6发表: 2008年 FROSTY...
FIG. 6A is a 2D graphical depiction of structural elements that make up a hypothetical net, rendered in a manner that graphically overlays sensitivities (e.g., of the circuit design characteristic being modeled, such as “RC delay”) to each individual parasitic. For example, as indicated by...
In one embodiment, since the multiplexer device313introduces an inherent delay in the system300, the integrated circuit301further includes an additional buffer stage δ314, prior to the data buffer device311, which receives the data input signal321and permits equalizing the delays and signal swings ...
This can add significant overhead to the router (e.g., delay and additional hardware and software) to change even just one policy statement in a given policy. If the CAM array is not loaded correctly, either upon initialization or upon change, addition or removal of a policy statement, an...