von Arnim K et al (2007) A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM. In: Symposium on VLSI technology digest of technical papers, pp 106-107
The problem of minimizing the number of transmissions for a multicast transmission under the condition that the packet delay is minimum in single-hop wavel... HC Lin,CH Wang - 《Photonic Network Communications》 被引量: 37发表: 2002年 Experimental demonstration of four-terminal magnetic logic dev...
ImpactofRiseTimeonDelay DynamicPower电容充电“0”电容放电“1” DynamicPowerDissipationVinVoutCLVdd 降低动态功耗降低电压VDD降低晶体管尺寸C降低节点翻转速率 ShortPower直流通路 ShortPowerShortcircuitcurrentgoestozeroiftfalltrise,butcan’tdothisforcascadelogic,so...In负载很大 ...
Elmore delay has been widely used to estimate interconnect delays in the performance-driven synthesis and layout of very-large-scale-integration (VLSI) rou... Kahng,B A.,Muddu,... - 《IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems》 被引量: 347发表: 1997年 Clock...
Exhibition-of-Master-Wan-Ko-Yee's-Amazing-Achievement-in-the-Form-of-World-Class-Treasures 热度: BS 449-1969 The Use of Structural Steel in Building - Part 2 - Metric units 热度: Long Nguyen. The Dynamics of Float, Logic, Resource Allocation, and Delay Timing in Forensic Schedule Analysis...
As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay... A Hirata,H Onodera,K Tamaru - 《Ieice Transactions on Fundamentals of Electronics Communications & Computer Sciences》 被引量: 9发表: 1998...
We propose a new type of SOI inverter gate which has considerably shortened circuit delay with similar energy consumption in the conventional SOI CMOS circuit at low voltage operation. It uses the positive-body bias effect that enhances drain currents when the body is biased positively. The ...
FIG. 38 shows the worst case delay in the inverter chain when the output of I1 changes from zero toV M 1 + LSB 2 , where it is clear that the effect of I2 to I5 on speed is negligible because they are biased by a larger overdrive voltage. FIGS. 38 and 39 compare ...
4.1 Active Power Consumption and Delay Overhead The active power consumption of the domino circuits is shown in Figs. 11 and 12 for 25 and 110 °C, respectively. The results show that active power in the lector with diode-footed inverter circuits is reduced compared with that for the footer...
VLSI Design EE213 VLSI DesignStephen Daniels 2003 Vdd Vss Vo Vin D S D S Pull-Up is always on – Vgs = 0; depletion Pull-Down turns on when Vin > Vt NMOS Depletion Mode Transistor Pull - Up Vt V0 Vdd Vi With no current drawn from outputs, Ids for both transistors is equal Non...