The phase detector and the oscillator of the control circuit can be constructed in VLSI technology as a single integrated circuit. Then a further digital module is allocated to this complex integrated module to form a sequential combinational logic system, programmable logic network, or a read-only...
INTEGRATED CIRCUIT INCLUDING CLOCK-GATED SYNCHRONIZER FOR LOW POWER, AND DATA PROCESSING SYSTEM INCLUDING SAME An integrated circuit is disclosed. The integrated circuit includes a delay circuit which receives and delays an asynchronous input signal; a first flip-fl... TK Shin,JP Park,SH Shin,.....
et al., “Clock Buffer Chip with Absolute Delay Regulation Over Process and Environmental Variations”, IEEE Custom Integrated Circuits Conference, 1992, pp. 25.2.1-25.2.5. Yoshimura, T. et al. “A 622-Mb/s Bit/Frame Synchronizer for High-Speed Backplane Data Communication”, IEEE Journal ...
3337747Analogue phase and frequency synchronizer for data communications1967-08-22Krasnick et al.307/262 Primary Examiner: ROSEEN, RICHARD R Attorney, Agent or Firm: J. MICHAEL ANGLIN (ROCHESTER, MN, US) Claims: We claim as our invention: ...
1. A master reset and synchronizer circuit comprising: A. state machine circuitry having a data in input, a reset input, a clock input, an enable output and a master reset output, the state machine circuitry having plural states that are sequentially stepped through in response to changes on...
5.The method of claim 4 wherein the skew on the first channel is adjusted by programming a programmable delay circuit coupled to the first channel. 6.The method of claim 4 wherein the act of adjusting the skew on the first channel is performed during start-up of a device that includes ...
EP0476585 Reference delay generator and electronic device using the same. EP0655741 Memory device and serial-parallel data transform circuit. EP0655834 Delay circuit using capacitor and transistor. EP0680049 Synchronizer. EP0703663 Programmable digital delay unit EP0704848 Semiconductor pipeline memory devic...