Quaternary adderQuaternary multiplexerQuaternary successorQuaternary predecessorUsing multi-valued logic (MVL) can reduce the chip area and connections which have direct effect on power consumption. Recently, according to the high ability of nanotechnology in designing MVL, some researchers have focused on ...
Simulation of 32 bit multiplier is carried out using modelsim SE PLUS 6.5b and synthesis is done using Xilinx tool.C.DhivyaM.ThiruppathiM.Nargeesh BanuD.Maheswari
Full adderEnergy recovery CMOS and Transmission gate multiplexerAn energy-efficient single bit full adder based on energy recovery CMOS XOR/XNOR using Clocked Adiabatic Logic (CAL), 2N-2N2P and transmission gate multiplexerKumar, ManojK. Arya, Sandeep...
MultiplexerAdder, CMOS (complementary metal oxide semiconductor)With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn't decrease at same rate as gates are increased...
OPTIMIZATION OF LOW POWER ALU USING NOVEL FULL ADDER AND PASS TRANSISTOR LOGIC BASED MULTIPLEXERAn Optimized compensation strategy for two-stage CMOS OTA has been proposed for a high frequency OPAMP design. Here, the slew rate and bandwidth has been increased by employing thin and long transistors...
LOW POWER 4-BIT ARITHMETIC LOGIC UNIT USING FULL-SWING GDI TECHNIQUE BASED FULL ADDER AND MULTIPLEXERPower dissipation and area of the circuit are the main issues in the electronics industry, this paper provides a design of 4-Bit Arithmetic Logic Unit (ALU) using Full-Swing GDI Technique, ...