Full Subtractor using 4X1 Multiplexer The execution of subtraction can be done through the two’s complement method. Thus we require utilizing a 1-XOR gate which is used to invert 1-bit & include one into carry bit. The output of DIFFERENCE is similar to the output SUM in the full adder...
The proposed ALU design consists of 2x1 Multiplexer, 4x1 Multiplexer and low power Full Adder cell to realize the arithmetic and logic operations. Simulations are performed by using MICROWIND 3.5 tool using Verilog file generated using DSCH 3.5, and implemented on CMOS 65nm technology. At first...
Quaternary adderQuaternary multiplexerQuaternary successorQuaternary predecessorUsing multi-valued logic (MVL) can reduce the chip area and connections which have direct effect on power consumption. Recently, according to the high ability of nanotechnology in designing MVL, some researchers have focused on ...
Full adderEnergy recovery CMOS and Transmission gate multiplexerAn energy-efficient single bit full adder based on energy recovery CMOS XOR/XNOR using Clocked Adiabatic Logic (CAL), 2N-2N2P and transmission gate multiplexerKumar, ManojK. Arya, Sandeep...
Simulation of 32 bit multiplier is carried out using modelsim SE PLUS 6.5b and synthesis is done using Xilinx tool.C.DhivyaM.ThiruppathiM.Nargeesh BanuD.Maheswari
OPTIMIZATION OF LOW POWER ALU USING NOVEL FULL ADDER AND PASS TRANSISTOR LOGIC BASED MULTIPLEXERAn Optimized compensation strategy for two-stage CMOS OTA has been proposed for a high frequency OPAMP design. Here, the slew rate and bandwidth has been increased by employing thin and long transistors...
Five new multiplexer-based architectures for 1-bit full adder cell design are presented. Implementing with the pass-gate CMOS multiplexer, results in five distinct adders. Those adder cells along with the conventional 28-transistor CMOS adder are tested using H-Spice under 6 different frequencies ...
MultiplexerAdder, CMOS (complementary metal oxide semiconductor)With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn't decrease at same rate as gates are increased...