On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a ...
On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a ...
Verilog Event-Driven Simulation Structure vs. Behavior Timing Model and Event-Driven Simulation Delays Instantiation Procedural Models Scheduling Summary Material from The Verilog Hardware Description Language, By Thomas and Moorby, Kluwer Academic Publishers ...
A race condition is a flaw in a system or process that is characterized by an output that exhibits an unexpected dependenceon the relative timing or ordering of events. It has two types: Hardwareracesand simulation induced races (unavoidable for event-driven simulation algorithm used by Verilog)....
MDCSIM: A COMPILED EVENT-DRIVEN MULTIDELAY SIMULATOR Introduction. As the design of a circuit proceeds, it is necessary to simulate circuit's behavior more and more accurately. In particular, more and more accurate timing models are needed. During the final phases of the design it is usually ...
event driven simulationdelay modelsembedded timing analyserThis papers describes SHC-SLX, a new VLSI simulator based on the cooperation of two different mechanisms, levelized compiled code and event driven simulation. The compiled code mechanism is different from previously levelized compiled code ...
Event-driven observer-based output feedback control for linear systems This paper concerns the problem of event-driven observer-based output feedback control of linear systems. Contrary to normal sampled-data control systems, ... J Zhang,F Gang - 《Automatica A Journal of Ifac the International ...
This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the syste...
More specifically, we distinguish time-driven and event-driven sequential simulations. In a time-driven sequential simulation, the events are grouped into lists of activities corresponding to timing cycles, and the time is updated at the end of each cycle; that is, the starting time of the ...
This chapter describes event-driven circuits. There are many sequential circuits that are driven by events rather than by a train of clock pulses. In this case, it is the event that drives the logic and as the events are irregular in occurrence such a circuit is referred to as an asynchron...